| CPC H04W 52/365 (2013.01) [H04L 5/0007 (2013.01); H04L 5/0053 (2013.01); H04W 72/0473 (2013.01)] | 16 Claims |

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1. An integrated circuit to control a process, the process comprising:
computing a first power headroom (PHR), the first PHR being obtained by subtracting a transmit power for a physical uplink shared channel (PUSCH) and a transmit power for a physical uplink control channel (PUCCH) from a maximum transmit power, wherein a number of bits for the first PHR equals a number of bits for a second PHR that is obtained by subtracting the transmit power for the PUSCH from the maximum transmit power, responsive to a configuration of transmitting the PUSCH simultaneously with the PUCCH; and
transmitting the first PHR, responsive to the configuration of transmitting the PUSCH simultaneously with the PUCCH.
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