| CPC H04W 12/122 (2021.01) [H04L 5/0053 (2013.01); H04W 12/108 (2021.01); H04W 72/20 (2023.01)] | 19 Claims |

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1. An apparatus comprising:
at least one processor; and
at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to perform:
transmitting a transport block, TB, via sidelink, SL, communication,
receiving a feedback in response to the transmitted TB,
storing information contained in the transmitted TB upon receiving said feedback,
receiving a status report comprising information associated with the TB, and
comparing said information contained in the status report with said stored information contained in the transmitted TB in order to identify an attacker based on discrepancy between said information contained in the status report and said stored information contained in the transmitted TB.
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