US 12,231,833 B2
Sensor module
Ralph Steiner Vanha, Stäfa (CH); Samuel Fuhrer, Stäfa (CH); Marcel Pluess, Stäfa (CH); and Ulrich Bartsch, Stäfa (CH)
Assigned to SENSIRION AG, Stäfa (CH)
Appl. No. 16/979,826
Filed by SENSIRION AG, Stäfa (CH)
PCT Filed Feb. 28, 2019, PCT No. PCT/EP2019/055019
§ 371(c)(1), (2) Date Sep. 10, 2020,
PCT Pub. No. WO2019/174925, PCT Pub. Date Sep. 19, 2019.
Claims priority of application No. 18161279 (EP), filed on Mar. 12, 2018.
Prior Publication US 2021/0044877 A1, Feb. 11, 2021
Int. Cl. H04Q 9/00 (2006.01); G01N 33/00 (2006.01); G06F 1/04 (2006.01); G06F 13/40 (2006.01)
CPC H04Q 9/00 (2013.01) [G01N 33/0022 (2013.01); G01N 33/0036 (2013.01); G01N 33/0073 (2013.01); G06F 1/04 (2013.01); G06F 13/40 (2013.01); H04Q 2209/30 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A sensor module, comprising:
a master sensor unit configured to sense a first environmental parameter;
a slave sensor unit configured to sense a second environmental parameter;
a common substrate on which the master sensor unit and the slave sensor unit are mounted; and
a digital bus interface for a communication between the master sensor unit and the slave sensor unit,
wherein the master sensor unit comprises a non-volatile memory configured to store calibration data and configuration data of the master sensor unit and the slave sensor unit,
wherein the master sensor unit is embodied as a first chip, and the slave sensor unit is embodied as a second chip,
wherein the master sensor unit and the slave sensor unit are configured to operate synchronously, based on a common clock with a common clock period and common phase for each sensor unit,
wherein the master sensor unit is configured to supply the common clock to the slave sensor unit,
wherein the common clock and a reset signal are supplied to the slave sensor unit via a combined signal over the digital bus interface on a single pin, and
wherein a reset pulse is derived from the combined signal in the slave sensor unit if the common clock period deviates from a nominal common clock period in a defined way.