| CPC H04N 19/31 (2014.11) [H04N 19/172 (2014.11); H04N 19/70 (2014.11)] | 17 Claims |
|
1. An encoder comprising:
circuitry; and
memory coupled to the circuitry, wherein
in operation, the circuitry:
encodes pictures in an encoding order according to temporal scalability that specifies temporal layers; and
adds, to a bitstream, information indicating whether coded picture buffer (CPB) removal timings of lower pictures in one or more first temporal layers in a first case are identical to CPB removal timings of the lower pictures in a second case, the one or more first temporal layers being lower than or equal to a lower temporal layer lower than a higher temporal layer among the temporal layers, the first case being a case in which the one or more first temporal layers are to be decoded, the second case being a case in which second temporal layers lower than or equal to the higher temporal layer are to be decoded,
one or more higher pictures in the higher temporal layer are placed between two adjacent lower pictures among the lower pictures in the encoding order,
a total number of the one or more higher pictures placed between the two adjacent lower pictures is n−1, where n is an integer greater than 1 and denotes a ratio of a second frame rate in the second case to a first frame rate in the first case, and
when the n is not equal to 2, the information indicates that the CPB removal timings of the lower pictures in the first case are not identical to the CPB removal timings of the lower pictures in the second case.
|