| CPC H04L 9/3278 (2013.01) [H03K 3/0315 (2013.01); H03K 3/84 (2013.01)] | 20 Claims |

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19. A physical unclonable function device, comprising:
a first signal generating circuit configured to generate a first clock signal of n-th period according to a control signal of the n-th period and an input signal of the n-th period, where n is an integer greater than or equal to 2;
a second signal generating circuit configured to generate a second clock signal of the n-th period according to the control signal of the n-th period and the input signal of the n-th period;
an output circuit configured to output an output signal of the n-th period according to the first clock signal of the n-th period and the second clock signal of the n-th period; and
a control circuit configured to process an initial control signal of the n-th period to obtain the control signal of the n-th period according to a reference value, the reference value comprising a logic level of an output signal of (n−1)-th period, wherein:
the first signal generating circuit comprises a first time-average-frequency direct period synthesis (TAF-DPS) circuit, and the second signal generating circuit comprises a second TAF-DPS circuit; and
the control signal comprises a control word, and the initial control signal comprises an initial control word, wherein the initial control word is C=F+r, where F is an integer, and r is a decimal greater than 0 and smaller than 1, and the control word of the n-th period is C(n) which is obtained by performing a mathematical operation on the reference value and at least one of F or r.
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