US 12,231,544 B2
Method and apparatus with homomorphic encryption
Jong-Seon No, Seoul (KR); Yongwoo Lee, Seoul (KR); and Young-Sik Kim, Gwangju (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); Seoul National University R&DB Foundation, Seoul (KR); and Industry Academic Cooperation Foundation, Chosun University, Gwangju (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR); Seoul National University R&DB Foundation, Seoul (KR); and Industry Academic Cooperation Foundation, Chosun University, Gwangju (KR)
Filed on Nov. 28, 2023, as Appl. No. 18/521,187.
Application 18/521,187 is a continuation of application No. 17/516,924, filed on Nov. 2, 2021, granted, now 11,870,889.
Claims priority of application No. 10-2021-0024262 (KR), filed on Feb. 23, 2021; and application No. 10-2021-0062640 (KR), filed on May 14, 2021.
Prior Publication US 2024/0106632 A1, Mar. 28, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/08 (2006.01); G06F 7/523 (2006.01); G06F 7/76 (2006.01); G06F 17/16 (2006.01); H04L 9/00 (2022.01); H04L 9/06 (2006.01)
CPC H04L 9/0825 (2013.01) [G06F 7/523 (2013.01); G06F 7/766 (2013.01); G06F 17/16 (2013.01); H04L 9/008 (2013.01); H04L 9/0618 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A processor-implemented method with homomorphic encryption, the method comprising:
receiving a first ciphertext corresponding to a first modulus;
generating a second ciphertext corresponding to a second modulus by performing modulus raising on the first ciphertext; and
performing bootstrapping by encoding the second ciphertext using a commutative property and an associative property of operations included in a rotation operation, including after adding a result of multiplications associated with the second ciphertext, performing a modulus down operation on a result of the adding, performing a decompose operation on a result of performing a rescaling operation on the second ciphertext, and performing a sum of multiplications on a result of the decompose operation.