US 12,231,530 B2
Method for performing power disturbing operation to reduce success rate of cryptosystem power analysis attack, cryptosystem processing circuit, and electronic device
Yuefeng Chen, Suzhou (CN)
Assigned to Realtek Semiconductor Corp., HsinChu (TW)
Filed by Realtek Semiconductor Corp., HsinChu (TW)
Filed on Aug. 11, 2022, as Appl. No. 17/885,581.
Claims priority of application No. 202210068877.9 (CN), filed on Jan. 20, 2022.
Prior Publication US 2023/0231696 A1, Jul. 20, 2023
Int. Cl. H04L 9/00 (2022.01); H04L 9/08 (2006.01)
CPC H04L 9/003 (2013.01) [H04L 9/0869 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method for performing a power disturbing operation to reduce a success rate of a cryptosystem power analysis attack, comprising:
utilizing a random number generating circuit to generate at least one random number;
generating a plurality of power disturbing parameters corresponding to a plurality of bit calculation phases, respectively, according to the at least one random number, wherein the plurality of bit calculation phases represent a plurality of cryptosystem processing phases related to a predetermined cryptosystem, and the plurality of bit calculation phases correspond to a plurality of private key bits of a private key, respectively; and
according to the plurality of power disturbing parameters, enabling at least one integrated clock gating circuit of a plurality of integrated clock gating circuits in the plurality of bit calculation phases, respectively, to utilize power corresponding to the plurality of power disturbing parameters to perform the power disturbing operation in the plurality of bit calculation phases, respectively;
wherein a plurality of target circuits are clocked by the plurality of integrated clock gating circuits, respectively, and power of each of the plurality of target circuits is changed based on enablement of a corresponding integrated clock gating circuit; and the plurality of target circuits includes at least one of a processor, a memory controller, a communication interface circuit and a true random number generator of an electronic device to which the predetermined cryptosystem corresponds.