	US 12,231,528 B2
	Apparatus for correcting error of clock signal
Byongmo Moon, Suwon-si (KR); Jeonghyeok You, Suwon-si (KR); Seongook Jung, Suwon-si (KR); Taeryeong Kim, Suwon-si (KR); and Hohyun Chae, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and UIF (University Industry Foundation), Yonsei University, Seoul (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 14, 2023, as Appl. No. 18/197,079.
Claims priority of application No. 10-2022-0142864 (KR), filed on Oct. 31, 2022.
Prior Publication US 2024/0146498 A1, May 2, 2024
Int. Cl. H04L 7/00 (2006.01); G06F 1/04 (2006.01); H03K 3/017 (2006.01); H03K 3/037 (2006.01); H03K 5/14 (2014.01); H03K 5/00 (2006.01); H03K 19/20 (2006.01)

CPC H04L 7/0016 (2013.01) [G06F 1/04 (2013.01); H03K 3/017 (2013.01); H03K 3/037 (2013.01); H03K 5/14 (2013.01); H03K 2005/00078 (2013.01); H03K 19/20 (2013.01)]

20 Claims

1. An apparatus for correcting an error of a clock signal, the apparatus comprising:

a phase adjuster configured to correct an error of half-rate clock signals based on an error correction signal, and to output an error-corrected clock signal;

a phase splitter configured to output a plurality of quadrature clock signals from the error- corrected clock signal;

an error detector configured to:

output an internal clock signal based on one of the plurality of quadrature clock signals,

select two quadrature clock signals among the plurality of quadrature clock signals based on a clock selection signal,

detect errors of the two quadrature clock signals based on an error check signal, and

output a correction request signal; and

a controller configured to:

output a mode selection signal and the clock selection signal based on the internal clock signal, and

output the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.