CPC H04L 7/0012 (2013.01) [H04L 7/0037 (2013.01); H04L 7/06 (2013.01); G06F 1/12 (2013.01)] | 14 Claims |
1. An apparatus comprising:
a clock generator configured to determine a sampling clock based on a received input clock and a clock offset;
a clock data recovery (CDR) circuit configured to:
determine a phase of the input clock; and
determine CDR codes based on the determined phase and sampled data;
logic configured to:
record a first CDR code of the CDR codes at a first time;
record a second CDR code of the CDR codes at a second time subsequent to the first time; and
determine a calibrated offset based on the first CDR code and the second CDR code; and
an adder configured to determine the clock offset according to the CDR codes and the calibrated offset.
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