US 12,231,526 B2
Method and timing recovery circuit for recovering a sampling clock from a serial data stream encoded using PAM
Thomas Hocker, Dresden (DE); and Sebastian Hoeppner, Dresden (DE)
Assigned to SILICONALLY GMBH, Dresden (DE)
Appl. No. 18/040,371
Filed by SILICONALLY GMBH, Dresden (DE)
PCT Filed Aug. 2, 2021, PCT No. PCT/EP2021/071581
§ 371(c)(1), (2) Date Feb. 2, 2023,
PCT Pub. No. WO2022/029085, PCT Pub. Date Feb. 10, 2022.
Claims priority of application No. 20189884 (EP), filed on Aug. 6, 2020.
Prior Publication US 2024/0063996 A1, Feb. 22, 2024
Int. Cl. H04B 3/32 (2006.01); H04L 7/00 (2006.01)
CPC H04L 7/0004 (2013.01) [H04L 7/0062 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for recovering a sampling clock from a serial data stream encoded using Pulse-Amplitude-Modulation scheme, comprising the steps of:
sampling received data signals from the serial data stream by an analog-to-digital converter once per unit-interval using a sampling clock signal provided by a clock generating device providing a timing recovery loop control,
quantizing an incoming data samples with a slicer as corresponding detected symbols,
storing adjacent incoming data samples and the corresponding detected symbols to preserve data for phase error estimation,
applying a digital filter pattern decoder to a current and last detected symbols to determine if the sequence of current and last detected symbols can be used to estimate a phase offset of the sampling clock signal from an ideal sampling point and calculating the estimated phase error depending on a detected symbol pattern of four adjacent samples,
adjusting the phase of the sampling clock signal within the timing recovery loop control using the calculated estimated phase error, and
multiplying the estimated phase error with a weight factor to obtain an error signal.