US 12,231,375 B2
Latency reduction in TDD systems with carrier aggragation
Thomas Fehrenbach, Berlin (DE); Dennis Wieruch, Berlin (DE); Bernd Holfeld, Berlin (DE); Thomas Wirth, Kleinmachnow (DE); Cornelius Hellge, Berlin (DE); Lars Thiele, Berlin (DE); and Thomas Haustein, Potsdam (DE)
Assigned to Koninklijke Philips N.V., Eindhoven (NL)
Filed by KONINKLIJKE PHILIPS N.V., Eindhoven (NL)
Filed on Dec. 14, 2021, as Appl. No. 17/550,805.
Application 17/550,805 is a continuation of application No. 16/272,773, filed on Feb. 11, 2019, granted, now 11,223,467.
Application 16/272,773 is a continuation of application No. PCT/EP2017/070459, filed on Aug. 11, 2017.
Claims priority of application No. 16183899 (EP), filed on Aug. 11, 2016.
Prior Publication US 2022/0109554 A1, Apr. 7, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 5/14 (2006.01); H04L 5/00 (2006.01); H04W 56/00 (2009.01); H04W 72/0446 (2023.01); H04W 72/0453 (2023.01); H04W 74/0833 (2024.01)
CPC H04L 5/1469 (2013.01) [H04L 5/001 (2013.01); H04L 5/0094 (2013.01); H04L 5/0098 (2013.01); H04W 56/001 (2013.01); H04W 72/0446 (2013.01); H04W 72/0453 (2013.01); H04W 74/0833 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A transceiver comprising:
a processor circuit; and
a memory circuit,
wherein the memory circuit is arranged to store instructions,
wherein the instructions are executable by the processor circuit,
wherein the processor circuit is arranged to receive instructions to configure a plurality of time-division duplex carriers,
wherein the processor circuit is arranged to aggregate at least two of the plurality of time-division duplex carriers to produce aggregated time-division duplex carriers,
wherein the processor circuit is configured to cause the transceiver to perform wireless data communication with a first third-party device via the aggregated time-division duplex carriers;
wherein the plurality of time-division duplex carriers comprises a temporal distribution of uplink times and a temporal distribution of downlink times, wherein the processor circuit is arranged to blank subcarriers at an edge of a frequency band of at least a first of the time-division duplex carriers,
wherein the first of the time-division duplex carriers is spectrally adjacent to at least a first of the aggregated time-division duplex carriers,
wherein the first of the time-division duplex carriers comprises a second of the aggregated time-division duplex carriers, or a second of the time-division duplex carriers,
wherein the transceiver communicates with a second third-party device using the second of the time-division duplex carriers.