US 12,231,304 B2
Efficient resource allocation for service level compliance
Rameshkumar Illikkal, Folsom, CA (US); Anna Drewek-Ossowicka, Gdansk (PL); Dharmisha Ketankumar Doshi, Folsom, CA (US); Qian Li, Stanford, CA (US); Andrzej Kuriata, Gdansk (PL); Andrew J. Herdrich, Hillsboro, OR (US); Teck Joo Goh, Saratoga, CA (US); Daniel Richins, Orem, UT (US); Slawomir Putyrski, Gdynia (PL); Wenhui Shu, Shanghai (CN); Long Cui, Shanghai (CN); Jinshi Chen, Shanghai (CN); and Mihai Daniel Dodan, Bucharest (RO)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 18/037,964
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 21, 2020, PCT No. PCT/CN2020/138138
§ 371(c)(1), (2) Date May 19, 2023,
PCT Pub. No. WO2022/133690, PCT Pub. Date Jun. 30, 2022.
Prior Publication US 2024/0015080 A1, Jan. 11, 2024
Int. Cl. H04L 41/5019 (2022.01); G06F 9/50 (2006.01)
CPC H04L 41/5019 (2013.01) [G06F 9/5011 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A hardware processor comprising:
one or more processor cores and an uncore collectively supporting simultaneous execution of multiple workloads; and
within the uncore, an intelligent resource manager to control, during execution of a primary workload among the multiple workloads, allocation of one or more shared microarchitecture resources of the one or more processor cores and the uncore to optimize the allocation of the one or more shared microarchitecture resources subject to enforcing a hardware service level objective (SLO) received as part of an instruction set for the primary workload, the hardware SLO comprising a target value of an SLO metric derived from a performance guarantee associated with the primary workload pursuant to a service level agreement (SLA).