US 12,231,283 B1
System and method for using FPGA look-up table as quadrature digital correlator
William B. Sorsby, Cedar Rapids, IA (US)
Assigned to Rockwell Collins, Inc., Cedar Rapids, IA (US)
Filed by Rockwell Collins, Inc., Cedar Rapids, IA (US)
Filed on Aug. 8, 2023, as Appl. No. 18/231,458.
Int. Cl. H04L 27/38 (2006.01)
CPC H04L 27/389 (2013.01) 20 Claims
OG exemplary drawing
 
1. A system for correlating a received signal, the system comprising;
an antenna configured to receive the received signal;
a controller comprising:
a field programmable gate array (FPGA) comprising a plurality of look-up tables (LUTs);
a plurality of registers for storing and manipulating data, the plurality of registers coupled to the plurality of LUTs and comprising:
a known reference register configured to store known binary values of a known reference sequence;
a secondary reference register configured to store secondary reference values;
an in-phase register configured to store in-phase binary values of the received signal; and
a quadrature register configured to store quadrature binary values of the received signal,
wherein each LUT is configured to receive Boolean inputs from the known reference register, the secondary reference register, the in-phase register, and the quadrature register and to output correlation results based on the Boolean inputs.