US 12,231,232 B2
Physical coding sublayer with modified bit ordering to improve error burst resiliency
Adee O. Ran, Maayan Baruch (IL)
Assigned to CISCO TECHNOLOGY, INC., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Dec. 21, 2022, as Appl. No. 18/085,698.
Claims priority of provisional application 63/358,264, filed on Jul. 5, 2022.
Prior Publication US 2024/0014927 A1, Jan. 11, 2024
Int. Cl. H04L 1/00 (2006.01)
CPC H04L 1/0041 (2013.01) [H04L 1/0045 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method comprising:
for each forward error corrected (FEC) codeword of a plurality of FEC codewords of data to be transmitted over a channel, obtaining a symbol from each logical lane of a plurality of logical lanes to which the plurality of FEC codewords have been multiplexed;
storing bits for the symbol from each logical lane of the plurality of logical lanes into a memory; and
re-ordering bits stored in the memory according to a mapping that permutes the bits stored in memory to produce a re-ordered block of bits distributed to a plurality of modified logical lanes equal in number to the plurality of logical lanes and the plurality of modified logical lanes are bit-multiplexed to at least one physical lane, resulting in the at least one physical lane obtaining a sequence of groups of bits for a symbol from one FEC codeword followed by a sequence of groups of bits for a symbol from another FEC codeword.