| CPC H04B 7/15507 (2013.01) [H04B 7/0617 (2013.01)] | 30 Claims |
|
1. An apparatus for wireless communication, comprising:
one or more memories; and
one or more processors coupled to the one or more memories, the one or more processors configured to cause the apparatus to:
receive, from a control node, a configuration that indicates to convert an incoming signal from an analog domain to a digital domain and indicates a plurality of digital processing operations comprising a processing of digital information, wherein the plurality of digital processing operations is selected from a plurality of digital processing options comprising two or more of:
a conversion of the incoming signal from the analog domain to the digital domain,
a performance of a fast Fourier transform (FFT) on a plurality of time domain in-phase and quadrature (IQ) samples associated with the incoming signal,
a performance of a resource element (RE) demapping procedure on a plurality of tones associated with the incoming signal,
a demodulation of a set of stabilized REs associated with the incoming signal, or
a decoding of a set of descrambled REs associated with the incoming signal;
receive a first signal;
perform the plurality of digital processing operations on the first signal to generate a second signal, wherein the second signal comprises a re-generated version of the first signal; and
transmit the second signal.
|