US 12,231,142 B2
Oversampled analog to digital converter
Amit Kumar Gupta, Frisco, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 27, 2022, as Appl. No. 17/874,750.
Claims priority of provisional application 63/327,079, filed on Apr. 4, 2022.
Prior Publication US 2023/0318615 A1, Oct. 5, 2023
Int. Cl. H03M 3/00 (2006.01); H03M 1/12 (2006.01); H03M 1/20 (2006.01); H03M 1/46 (2006.01)
CPC H03M 1/462 (2013.01) [H03M 1/20 (2013.01); H03M 1/466 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An analog-to-digital converter (ADC), comprising:
an input adapted to receive an input voltage;
an output adapted to provide an output signal;
a comparator having a first input coupled to the input of the ADC, a second input, and an output, the comparator configured to provide a comparator output signal at the output responsive to the input voltage and a digital-to-analog converter (DAC) output voltage;
a successive-approximation register (SAR) circuit having an input coupled to the output of the comparator and including a SAR that is configured to store an n-bit digital code that is initialized to an initial value at a beginning of a conversion phase of the ADC, wherein the SAR circuit is configured to:
provide the n-bit digital code as an output signal at an output of the SAR circuit, the output of the ADC coupled to the output of the SAR circuit; and
update the n-bit digital code responsive to the comparator output signal, wherein the output signal of the ADC is responsive to the n-bit digital code at an end of the conversion phase; and
a DAC configured to provide the DAC output voltage responsive to the n-bit digital code and a reference voltage, wherein the DAC includes:
an m-bit capacitive DAC (CDAC) having a first input, having a second input coupled to the output of the SAR circuit, and having an output coupled to the second input of the comparator; and
an (n−m)-bit resistive DAC (RDAC) having an input coupled to the output of the SAR circuit and having an output coupled to the first input of the m-bit CDAC, the RDAC configured to provide an intermediate DAC voltage responsive to the n−m least-significant bits of the n-bit digital code and the reference voltage,
wherein the m-bit CDAC is configured to provide the DAC output voltage responsive to the m most-significant bits of the n-bit digital code, the intermediate DAC voltage, and the reference voltage.