US 12,231,137 B2
Hybrid analog-to-digital converter with inverter-based residue amplifier
Martin Kinyua, Cedar Park, TX (US); and Eric Soenen, Austin, TX (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/231,745.
Application 18/231,745 is a continuation of application No. 17/718,157, filed on Apr. 11, 2022, granted, now 11,770,125.
Application 17/718,157 is a continuation of application No. 17/146,056, filed on Jan. 11, 2021, granted, now 11,329,659.
Claims priority of provisional application 62/981,668, filed on Feb. 26, 2020.
Prior Publication US 2023/0412179 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/06 (2006.01)
CPC H03M 1/0602 (2013.01) 20 Claims
OG exemplary drawing
 
1. A physical unclonable function (PUF) generator comprising:
a plurality of PUF cells, wherein each of the plurality of PUF cells comprises a plurality of transistors;
a plurality of circuits wherein each of the plurality of circuits is coupled to each of the plurality of PUF cells respectively, wherein the plurality of circuits each is configured to monitoring a voltage level on a node on each of the plurality of PUF cells;
a population count circuit coupled to the plurality of circuits, wherein the population count circuit is configured to determine a first number of PUF cells having flipped logical states from a first logical state to a second logical state; and
an evaluation logic circuit having an input coupled to the population count circuit and an output coupled to the plurality of circuits, wherein the evaluation logic circuit is configured to compare the first number with a predetermined number of PUF cells, wherein a PUF signature is generated when the number of PUF cells that are at the second logical state are equal to or higher than the predetermined number of PUF cells.