US 12,231,134 B2
Method and apparatus for controlling clock cycle time
Eitan Rosen, Abirim (IL); and Oded Norman, Pardesia (IL)
Assigned to Marvell Asia Pte, Ltd., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Feb. 6, 2024, as Appl. No. 18/434,225.
Application 18/434,225 is a continuation of application No. 18/061,177, filed on Dec. 2, 2022, granted, now 11,936,394.
Application 18/061,177 is a continuation of application No. 17/679,999, filed on Feb. 24, 2022, granted, now 11,545,988, issued on Jan. 3, 2023.
Application 17/679,999 is a continuation of application No. 17/215,862, filed on Mar. 29, 2021, granted, now 11,296,712, issued on Apr. 5, 2022.
Application 17/215,862 is a continuation of application No. 16/887,963, filed on May 29, 2020, granted, now 10,998,910, issued on May 4, 2021.
Claims priority of provisional application 62/975,073, filed on Feb. 11, 2020.
Prior Publication US 2024/0178849 A1, May 30, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/03 (2006.01); H03K 5/13 (2014.01); H03L 5/00 (2006.01); H03L 7/099 (2006.01); H03L 7/16 (2006.01)
CPC H03L 7/16 (2013.01) [H03K 3/0315 (2013.01); H03K 5/13 (2013.01); H03L 5/00 (2013.01); H03L 7/0995 (2013.01); H03L 7/0996 (2013.01)] 35 Claims
OG exemplary drawing
 
1. A circuit comprising:
an agile ring oscillator (ARO) configured to generate high and low phases of cycles of an output clock; and
an ARO controller configured to control durations of the high and low phases of the output clock, independently, via first and second outputs to the ARO, respectively.