US 12,231,133 B2
Self-referenced delay cell-based time-to-digital converter
Anish Morakhia, Mountain View, CA (US)
Assigned to NVIDIA Corporation, Santa Clara, CA (US)
Filed by NVIDIA Corporation, Santa Clara, CA (US)
Filed on May 9, 2023, as Appl. No. 18/144,967.
Application 18/144,967 is a continuation of application No. 17/542,269, filed on Dec. 3, 2021, granted, now 11,683,043.
Prior Publication US 2023/0275587 A1, Aug. 31, 2023
Int. Cl. H03L 7/089 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/089 (2013.01) [H03L 7/0992 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A time-to-digital converter (TDC) circuit comprising:
control logic; and
a plurality of self-referenced delay cell circuits coupled to the control logic, wherein each self-referenced delay cell circuit of the plurality of self-referenced delay cell circuits comprises:
a first inverter coupled in series with a second inverter, the first inverter to receive a positive time signal representative of an incoming up signal;
a third inverter coupled in series with a fourth inverter, the third inverter to receive a negative time signal representative of an incoming down signal;
a first bank of capacitors coupled to a first node between the first inverter and the second inverter, wherein the first bank of capacitors is selectively controlled by a first control signal from the control logic; and
a second bank of capacitors coupled to a second node between the third inverter and the fourth inverter, wherein the second bank of capacitors is selectively controlled by a second control signal from the control logic; and
wherein the control logic is to:
generate a plurality of first control signals to selectively control the first bank of capacitors of the plurality of self-referenced delay cell circuits, wherein respective ones of the plurality of first control signals comprise an up value; and
generate a plurality of second control signals to selectively control the second bank of capacitors of the plurality of self-referenced delay cell circuits, wherein respective ones of the plurality of second control signals comprise a down value, and wherein the up values vary relative to the down values across the plurality of first and second control signals.