US 12,231,132 B2
Systems and methods for PLL duty cycle calibration
Karim M Megawer, San Diego, CA (US); Jongmin Park, San Diego, CA (US); and Thomas Mayer, Linz (AT)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Mar. 13, 2023, as Appl. No. 18/120,838.
Prior Publication US 2024/0313788 A1, Sep. 19, 2024
Int. Cl. H03L 7/081 (2006.01); H03K 5/156 (2006.01); H03L 7/083 (2006.01); H03L 7/087 (2006.01)
CPC H03L 7/081 (2013.01) [H03K 5/1565 (2013.01); H03L 7/0818 (2013.01); H03L 7/083 (2013.01); H03L 7/087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A transceiver, comprising:
receive circuitry;
transmit circuitry; and
a phase locked loop (PLL) coupled to the receive circuitry, the transmit circuitry, or both, the PLL comprising
a phase detector coupled to a reference clock generator and feedback circuitry,
duty cycle calibration circuitry coupled to an output of the phase detector,
duty cycle offset calibration circuitry coupled to the output of the phase detector, and
a delay element coupled to an output of the duty cycle offset calibration circuitry.