| CPC H03K 5/01 (2013.01) [H03L 7/08 (2013.01)] | 20 Claims |

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1. An electrical system, comprising:
a first chip having a first phase lock circuit and a first buffering circuit embedded within the first chip; and
a second chip having a second phase lock circuit and a second buffering circuit embedded within the second chip, wherein
the first phase lock circuit is configured to receive a first periodic signal having a first frequency;
the first buffering circuit is configured to receive a second periodic signal having the first frequency and configured to provide a third periodic signal having the first frequency by amplifying the second periodic signal, at an output terminal of the first chip;
the second phase lock circuit is configured to receive the third periodic signal from the first chip; and
the second buffering circuit is configured to receive a fourth periodic signal having the first frequency and generate a fifth periodic signal having the first frequency by amplifying the fourth periodic signal.
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