US 12,231,125 B1
Power efficient retention flip flop circuit
Sai Yaswanth Divvela, Andhra Pradesh (IN); Amit Verma, Telangana (IN); Basannagouda Reddy, San Jose, CA (US); and Deepak D. Sherlekar, Cupertino, CA (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by SYNOPSYS, INC., Sunnyvale, CA (US)
Filed on Jun. 12, 2023, as Appl. No. 18/208,753.
Int. Cl. H03K 3/037 (2006.01); H03K 3/012 (2006.01)
CPC H03K 3/037 (2013.01) [H03K 3/012 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first latch;
a second latch coupled to the first latch at an output terminal of the first latch; and
a third latch coupled to the second latch at an input terminal of the second latch, wherein the third latch comprises:
a first inverter and a second inverter, the first inverter being coupled between the input terminal of the second latch and an input terminal of the second inverter and the second inverter being coupled between an output terminal of the first inverter and an input terminal of the first inverter;
a first switch connecting the first inverter to a first voltage source;
a second switch connecting the first inverter to ground voltage;
a third switch connecting the second inverter to the first voltage source;
a fourth switch connecting the second inverter to the ground voltage; and
a fifth switch connecting the input terminal of the second latch and the input terminal of the first inverter.