US 12,231,124 B2
Hierarchical statisically multiplexed counters and a method thereof
Weihuang Wang, Los Gatos, CA (US); Gerald Schmidt, San Jose, CA (US); Srinath Atluri, Fremont, CA (US); Weinan Ma, San Jose, CA (US); and Shrikant Sundaram Lnu, San Jose, CA (US)
Assigned to Marvell Asia Pte, Ltd., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Nov. 1, 2023, as Appl. No. 18/500,091.
Application 18/500,091 is a division of application No. 17/591,546, filed on Feb. 2, 2022, granted, now 11,843,378.
Application 17/070,771 is a division of application No. 16/019,780, filed on Jun. 27, 2018, granted, now 10,840,912.
Application 16/019,780 is a division of application No. 15/202,428, filed on Jul. 5, 2016, granted, now 10,038,448.
Application 15/202,428 is a division of application No. 14/302,351, filed on Jun. 11, 2014, granted, now 9,413,357.
Application 17/591,546 is a continuation of application No. 17/070,771, filed on Oct. 14, 2020, granted, now 11,277,138.
Prior Publication US 2024/0063800 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 21/00 (2006.01); H03K 21/02 (2006.01); H03K 23/64 (2006.01); H04L 47/62 (2022.01); H04L 49/90 (2022.01); H03K 21/10 (2006.01); H03K 23/00 (2006.01)
CPC H03K 21/026 (2013.01) [H03K 23/64 (2013.01); H04L 47/62 (2013.01); H04L 49/9084 (2013.01); H03K 21/00 (2013.01); H03K 21/10 (2013.01); H03K 23/00 (2013.01); H03K 23/004 (2013.01); H03K 23/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A counter architecture implemented in a network device, the counter architecture comprising:
a mirrored shift logic; and
a hierarchy of levels of statistically multiplexed counters, wherein each level of the hierarchy of levels includes N counters arranged in rows having P base counters, and further wherein the mirrored shift logic extends the P base counters to a full width such that a full range of shifting is reduced.