US 12,231,121 B2
Multi-bit level shifter with shared enable signals
Sz-Han Chen, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsinchu (TW)
Filed on Dec. 9, 2022, as Appl. No. 18/063,731.
Claims priority of provisional application 63/297,265, filed on Jan. 7, 2022.
Prior Publication US 2023/0223937 A1, Jul. 13, 2023
Int. Cl. H03K 19/0185 (2006.01); H03K 3/037 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 3/037 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a control inverter, receiving a control signal to generate a reverse control signal, wherein the reverse control signal is an inverse of the control signal;
a first latch circuit, activated by the reverse control signal to convert a first input signal ranging from a first supply voltage to a ground into a first output signal ranging from a second supply voltage to the ground; and
a second latch circuit, activated by the reverse control signal to convert a second input signal ranging from the first supply voltage to the ground into a second output signal ranging from the second supply voltage to the ground, wherein the first supply voltage and the second supply voltage are different;
wherein the first latch circuit comprises a plurality of P-type transistors and a plurality of N-type transistors;
wherein the P-type transistors are arranged in a first direction, the N-type transistors are arranged in the first direction, and the P-type transistors and the N-type transistors are arranged in a second direction;
wherein the first direction and the second direction are orthogonal,
wherein a P-type guard ring surrounds the P-type transistors;
wherein an N-type guard ring surrounds the N-type transistors;
wherein the P-type guard ring and the N-type guard ring are arranged in the second direction and adjacent to each other.