US 12,231,120 B1
Apparatus, system, and method for improving latency or power consumption
Jagadeesh Anathahalli Singrigowda, Bengaluru (IN); Girish A S, Bengaluru (IN); Aniket Bharat Waghide, Bengaluru (IN); and Prasant Kumar Vallur, Bengaluru (IN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 30, 2022, as Appl. No. 17/855,562.
Int. Cl. H03K 19/00 (2006.01); G06F 1/3203 (2019.01); G06F 1/3212 (2019.01); G06F 1/3234 (2019.01); G06F 1/3296 (2019.01); G06K 15/00 (2006.01); H03K 3/037 (2006.01); H03K 19/17736 (2020.01)
CPC H03K 19/0016 (2013.01) [G06F 1/3203 (2013.01); G06F 1/3212 (2013.01); G06F 1/3234 (2013.01); G06F 1/3296 (2013.01); G06K 15/4055 (2013.01); H03K 3/037 (2013.01); H03K 19/17744 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, at a power-state processing circuit, a delayed power availability signal and a power-state signal indicating whether a processing unit is entering a low-power-state;
transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit;
storing, by the latching circuit and in response to the control signal, a state of a data signal at an input/output pad that is coupled to the processing unit;
bypassing, in response to exiting the low-power-state, a delay of the delayed power availability signal by asserting a non-delayed power availability signal; and
restoring, by the latching circuit and in response to the non-delayed power availability signal, the state of the data signal at the input/output pad.