US 12,231,119 B2
Lower voltage switching of current mode logic circuits
Steven Ernest Finn, Chamblee, GA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Mar. 30, 2020, as Appl. No. 16/834,316.
Application 16/834,316 is a continuation of application No. 15/993,725, filed on May 31, 2018, granted, now 10,644,699.
Prior Publication US 2020/0228119 A1, Jul. 16, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/00 (2006.01); H03K 19/0175 (2006.01); H03K 19/0944 (2006.01)
CPC H03K 19/0016 (2013.01) [H03K 19/001 (2013.01); H03K 19/0013 (2013.01); H03K 19/017554 (2013.01); H03K 19/09448 (2013.01)] 7 Claims
OG exemplary drawing
 
1. Apparatus comprising:
a circuit, the circuit including: a first transistor and a second transistor, each having a respective control terminal and respective first and second terminals, the control terminal of the first transistor is coupled to a first input terminal, the first terminal of the first transistor is coupled to a first voltage terminal, the first terminal of the second transistor is coupled to a first output terminal;
a first resistor having a first resistor terminal directly connected to the first input terminal and having a second resistor terminal directly connected to the first output terminal;
a first capacitor having a first capacitor terminal coupled to the second terminal of the first transistor and having a second capacitor terminal coupled to the first output terminal;
a third transistor having a respective control terminal and respective first and second terminals, the first terminal of the third transistor is coupled to the second terminal of the first transistor and the second terminals of the second and third transistors are coupled to a second voltage terminal;
fourth and fifth transistors, each having a respective control terminal and respective first and second terminals, the control terminal of the fourth transistor is coupled to a second input terminal, the first terminal of the fourth transistor is coupled to the first voltage terminal, the first terminal of the fifth transistor is coupled to a second output terminal, and the control terminals of the second and fifth transistors are coupled together;
a second resistor having a third resistor terminal directly connected to the second input terminal and having a fourth resistor terminal directly connected to the second output terminal;
a second capacitor having a third capacitor terminal coupled to the second terminal of the fourth transistor and having a fourth capacitor terminal coupled to the second output terminal; and
a sixth transistor having a respective control terminal and respective first and second terminals, its first terminal is coupled to the second terminal of the fourth transistor, the control terminals of the third and sixth transistors are coupled together, and the second terminals of the fifth and sixth transistors are coupled to the second voltage terminal;
wherein the circuit is a first circuit, the apparatus further comprising a second circuit including:
a first current mirror including seventh and eighth transistors each having respective control terminals coupled together;
a second current mirror coupled to the first current mirror, the second current mirror including ninth and tenth transistors each having respective control terminals coupled together and coupled to the control terminals of the second and fifth transistors;
a current source coupled between the seventh and eighth transistors and one of the transistors of the second current mirror; and
an eleventh transistor coupled to the first current mirror, the eleventh transistor having a respective control terminal coupled to the current source and the one of the transistors of the second current mirror.