US 12,231,117 B2
Integrated circuit and method of manufacturing same
Lei Pan, Hsinchu (TW); Yaqi Ma, Hsinchu (TW); Jing Ding, Hsinchu (TW); and Zhang-Ying Yan, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); TSMC CHINA COMPANY, LIMITED, Shanghai (CN); and TSMC NANJING COMPANY, LIMITED, Nanjing (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); TSMC CHINA COMPANY, LIMITED, Shanghai (CN); and TSMC NANJING COMPANY, LIMITED, Suzhou (CN)
Filed on Jul. 3, 2023, as Appl. No. 18/346,723.
Application 18/346,723 is a division of application No. 17/508,176, filed on Oct. 22, 2021, granted, now 11,695,413.
Claims priority of application No. 202111106999.4 (CN), filed on Sep. 22, 2021.
Prior Publication US 2023/0353143 A1, Nov. 2, 2023
Int. Cl. H01L 27/02 (2006.01); H03K 17/687 (2006.01)
CPC H03K 17/6872 (2013.01) [H01L 27/0251 (2013.01); H01L 27/0274 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a Schmitt trigger circuit, comprising:
a first set of transistors connected between a first voltage supply and an output node, the first voltage supply having a first supply voltage;
a second set of transistors connected between the output node and a second voltage supply different from the first voltage supply, the second voltage supply having a second supply voltage different from the first supply voltage;
a first feedback transistor connected to the output node, a first node between the first set of transistors, and a second node;
a first circuit electrically connected to the second node, the first voltage supply and the second voltage supply, and configured to supply the second supply voltage to the second node;
a second feedback transistor connected to the output node, a third node between the second set of transistors, and a fourth node; and
a second circuit electrically connected to the fourth node, the first voltage supply and the second voltage supply, and configured to supply the first supply voltage to the fourth node; and
a gate grounded NMOS (GGNMOS) transistor connected between the first voltage supply and the second voltage supply, and being in parallel with the Schmitt Trigger circuit.