US 12,231,114 B2
Methods and devices to improve switching time by bypassing gate resistor
Payman Shanjani, San Diego, CA (US); and Eric S. Shapiro, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Dec. 15, 2023, as Appl. No. 18/542,198.
Application 18/542,198 is a continuation of application No. 17/940,888, filed on Sep. 8, 2022, granted, now 11,855,611.
Application 17/940,888 is a continuation of application No. 16/951,838, filed on Nov. 18, 2020, granted, now 11,444,614, issued on Sep. 13, 2022.
Application 16/951,838 is a continuation of application No. 16/538,268, filed on Aug. 12, 2019, granted, now 10,848,141, issued on Nov. 24, 2020.
Application 16/538,268 is a continuation of application No. 15/376,471, filed on Dec. 12, 2016, granted, now 10,396,772, issued on Aug. 27, 2019.
Prior Publication US 2024/0235539 A1, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 17/0412 (2006.01)
CPC H03K 17/04123 (2013.01) 20 Claims
OG exemplary drawing
 
1. A switching circuit comprising:
an input terminal;
a plurality of main switches arranged in series, each main switch having a control terminal;
a common node connected to the control terminals of the main switches;
a bypass switch circuit comprising:
a first set of bypass switches arranged in series;
a second set of bypass switches arranged in series, and
a plurality of first bypass control resistors, each connected to a control terminal of a corresponding bypass switch in the first set of bypass switches, and a plurality of second bypass control resistors, each connected to a control terminal of a corresponding bypass switch in the second set of bypass switches, and
wherein:
each bypass switch in the first set is coupled to a corresponding bypass switch in the second set, and
the first set of bypass switches and the second set of bypass switches are connected between the input terminal and the common node.