US 12,231,106 B2
Apparatuses and methods for calibrating adjustable impedances of a semiconductor device
Dean Gans, Nampa, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Mar. 15, 2024, as Appl. No. 18/607,063.
Application 18/607,063 is a continuation of application No. 18/419,948, filed on Jan. 23, 2024.
Application 18/419,948 is a continuation of application No. 18/047,373, filed on Oct. 18, 2022, granted, now 11,916,527, issued on Feb. 27, 2024.
Application 18/047,373 is a continuation of application No. 17/119,664, filed on Dec. 11, 2020, granted, now 11,482,989, issued on Oct. 25, 2022.
Application 17/119,664 is a continuation of application No. 16/505,369, filed on Jul. 8, 2019, granted, now 10,868,519, issued on Dec. 15, 2020.
Application 16/505,369 is a continuation of application No. 15/834,892, filed on Dec. 7, 2017, granted, now 10,348,270, issued on Jul. 9, 2019.
Claims priority of provisional application 62/432,494, filed on Dec. 9, 2016.
Prior Publication US 2024/0223160 A1, Jul. 4, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 29/02 (2006.01); H03H 11/28 (2006.01); H03K 19/00 (2006.01); H04L 25/02 (2006.01); H03H 11/54 (2006.01)
CPC H03H 11/28 (2013.01) [G11C 7/10 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); H03K 19/0005 (2013.01); H03H 11/54 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory controller configured to cause a memory to apply new calibration results to programmable termination resistances by performing operations comprising:
provide a register read command to a register of a memory;
receive, responsive to the register read command, at least one bit from the register of the memory;
determine, based on a value of the at least one bit from the register of the memory, availability or unavailability of new calibration results of a calibration operation associated with the programmable termination resistances; and
provide a latch command to the memory when the value of the at least one bit in the register of the memory indicates the availability of the new calibration results, wherein the latch command is configured to cause the memory to apply the new calibration results to the programmable termination resistances.