| CPC H03F 3/607 (2013.01) [H03F 1/56 (2013.01); H03F 3/245 (2013.01); H03F 2200/255 (2013.01)] | 3 Claims |
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1. An optimization method of a harmonic control-based distributed power amplifier, wherein the harmonic control-based distributed power amplifier, comprises: an input artificial uniform transmission line (1), an output artificial non-uniform transmission line (2), and plural gain units (3), wherein two ports of the output artificial non-uniform transmission line (2) are respectively connected with reactive terminals (4), and in each gain unit (3), a gate electrode of a transistor is connected with an RC parallel resonant circuit, wherein the optimization method is carried out in the following steps:
at step 1, dividing a working frequency band into Δf1, Δf2 and Δf3, setting a fundamental frequency to f1, and obtaining an optimal fundamental wave load impedance Z10 by load pull, using Z10 as a second or third-order fixed harmonic load impedance of a frequency point within the Δf2 frequency band, wherein a class-J mode second-order harmonic load impedance of f1 is calculated in the following formula (1.1):
 wherein VDD is a voltage of a power supply, VK is a knee voltage of a transistor, Imax is a maximal drain current of a transistor −1≤α≤1 is a constant parameter, RoptB=2(VDD−VK)/Imax is an optimal fundamental wave load impedance of a class-B power amplifier (PA);
at step 2, setting the fundamental wave to f2, and fixing Z10 as a second-order harmonic load impedance, namely, Z22=Z10, and obtaining an optimal fundamental wave load impedance Z20 by load pull, wherein Z20 is affected by the second-order harmonic load impedance Z22;
at step 3, setting the fundamental frequency to f3, fixing Z10 as a third-order harmonic load impedance, namely, Z33=Z10, fixing Z20 as a second-order harmonic load impedance, namely, Z32=Z20, and obtaining an optimal fundamental wave load impedance Z30 by load pull, wherein Z30 is affected by the second-order harmonic load impedance Z32 and the third-order harmonic load impedance Z33;
at step 4, by substituting the optimal fundamental wave impedance into the following formula, calculating an initial value of a drain line impedance:
GCD(1)=GOPT(1) (0.2)
 wherein GCD(1) is an optimal characteristic conductance of a first-segment drain line, GOPT(1) is an optimal fundamental wave conductance of a first-level transistor, GCD(n) is an optimal characteristic conductance of an n-th-segment drain line, GDL is a drain terminating resistance, GOPT(n)=1/ROPT(n)=re(Zopt(n)) is an optimal fundamental wave conductance of an n-th-level transistor, and GOPT(k) is an optimal fundamental wave conductance of a k-th-level transistor;
determining an initial value of a gate line impedance in the following formula:
 wherein GCG(i) is an optimal characteristic conductance of an i-th-segment gate line, and GIN(k) is an input conductance of the k-th-level transistor;
further, an electrical length of the gate line and an electrical length of the drain line satisfy the following relationship, wherein θCG(i) is an electrical length of an i-th-segment gate line and θCD(i) is an electrical length of an i-th-segment drain line:
θCG(i)=θCD(i) (0.5)
at step 5, terminating the second-order harmonic impedance of the Δf1 frequency band to a pure reactance part to realize a class-J working mode, and adjusting the electrical lengths is satisfied, of the gate line and the drain line, and when the condition of θCG(i)=θCD(i) introducing reactance to offset an imaginary component of the optimal fundamental wave impedance so as to complete optimization on the harmonic control-based distributed power amplifier.
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