US 12,231,091 B1
Multiple transistor LNA MMIC design
Fawad Maqbool, Bohemia, NY (US)
Assigned to AmpliTech, Inc., Bohemia, NY (US)
Filed by AmpliTech, Inc., Bohemia, NY (US)
Filed on May 17, 2021, as Appl. No. 17/322,448.
Claims priority of provisional application 63/025,797, filed on May 15, 2020.
Int. Cl. H03F 1/02 (2006.01); H03F 1/26 (2006.01); H03F 1/56 (2006.01); H03F 3/187 (2006.01)
CPC H03F 1/26 (2013.01) [H03F 1/565 (2013.01); H03F 3/187 (2013.01); H03F 2200/255 (2013.01); H03F 2200/294 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An amplifier comprising:
an input of a first amplification stage that receives a signal;
a first field effect transistor (FET) of a plurality of FETS of the first amplification stage disposed on a substrate, wherein the input is coupled to the first FET through a first inductor, wherein the first FET amplifies the signal to output a first amplified signal through a second inductor and a capacitor to an output of the first amplification stage;
a second FET of the plurality of FETS of the first amplification stage disposed on the substrate, wherein the input is coupled to the second FET through a third inductor, wherein the second FET amplifies the signal to output a second amplified signal through a fourth inductor and the capacitor to the output;
a third FET of the plurality of FETS of the first amplification stage disposed on the substrate, wherein the input is coupled to the third FET through a fifth inductor, wherein the third FET amplifies the signal to output a third amplified signal through a sixth inductor and the capacitor to the output; and
the output of the first amplification stage that receives the first amplified signal and the second amplified signal and the third amplified signal through the capacitor, wherein the plurality of FETs are arranged in a parallel arrangement within the first amplification stage, wherein the plurality of FETs are each respectively tuned to different corner frequencies, wherein an effective gate width of the first amplification stage is greater than respective gate widths of respective gates of the plurality of FETs based on the parallel arrangement, wherein a noise figure of the first amplification stage is lower than respective noise figures of the plurality of FETs based on the parallel arrangement and the different corner frequencies, and wherein a return loss of the first amplification stage is lower than respective return losses of the plurality of FETs based on the parallel arrangement and the different corner frequencies.