| CPC H03D 7/1458 (2013.01) [H03D 7/1441 (2013.01)] | 4 Claims |
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1. A switch circuit, comprising:
a transmission gate having two input/output (I/O) terminals, two gate control terminals and two base control terminals, and is configured to make the two I/O terminals conduct or not conduct with each other according to voltages of the two gate control terminals;
two base control sub-circuits, each comprising:
a first transistor having a first terminal electrically connected to a first one of the two I/O terminals, a second terminal electrically connected to a first node, and a control terminal electrically connected to a second node; and
a second transistor having a first terminal electrically connected to the first node, a second terminal electrically connected to a second one of the two I/O terminals, and a control terminal electrically connected to the second node;
a third transistor having a first terminal electrically connected a first one of the two base control terminals, a second terminal which is grounded, and a control terminal electrically connected a first one of the two gate control terminals;
a fourth transistor having a first terminal configured to receive a working voltage, a second terminal electrically connected to a second one of the two base control terminals, and a control terminal electrically connected to a second one of the two gate control terminals;
a fifth transistor having a first terminal of the fifth transistor electrically connected to the first terminal of the first transistor of a first one of the two base control sub-circuits, a second terminal electrically connected to the second terminal of the first transistor of the first one of the two base control sub-circuits, and a control terminal electrically connected to the control terminal of the first transistor of a second one of the two base control sub-circuits; and
a sixth transistor having a first terminal of the sixth transistor electrically connected to the first terminal of the second transistor of the first one of the two base control sub-circuits, a second terminal electrically connected to the second terminal of the second transistor of the first one of the two base control sub-circuits, and a control terminal electrically connected to the control terminal of the second transistor of the second one of the two base control sub-circuits;
wherein the first node and the second node corresponding to one of the two base control sub-circuits are the first one of the two base control terminals and the second one of the two gate control terminals, respectively, and the first node and the second node of the other one of the two base control sub-circuits are the second one of the two base control terminals and the first one of the two gate control terminals, respectively.
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