US 12,231,059 B2
Method for controlling a multilevel inverter with a split DC link
Richard Grasböck, Wels-Thalheim (AT); Michael Rothboeck, Wels-Thalheim (AT); Roland Pieler, Wels-Thalheim (AT); and Harald Kreuzer, Wels-Thalheim (AT)
Assigned to Fronius International GmbH, Pettenbach (AT)
Appl. No. 17/919,294
Filed by Fronius International GmbH, Pettenbach (AT)
PCT Filed Apr. 19, 2021, PCT No. PCT/EP2021/060011
§ 371(c)(1), (2) Date Oct. 17, 2022,
PCT Pub. No. WO2021/213947, PCT Pub. Date Oct. 28, 2021.
Claims priority of application No. 20170373 (EP), filed on Apr. 20, 2020.
Prior Publication US 2023/0198421 A1, Jun. 22, 2023
Int. Cl. H02M 7/483 (2007.01); H02M 1/08 (2006.01); H02M 7/487 (2007.01)
CPC H02M 7/4833 (2021.05) [H02M 1/08 (2013.01); H02M 7/487 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for controlling a multilevel inverter having a DC link with at least two DC link capacitors that are connected to a switching stage with semiconductor switches for setting an output voltage or output current of the inverter according to a given setpoint value, comprising:
calculating a modulation signal with a modulation signal amplitude as an even harmonic signal of the output voltage (uAC) or output current (iAC) of the inverter, wherein the modulation signal is calculated from an actual electric power difference (Pdiff,act) of actual electric powers at the at least two DC link capacitors (CDC1, CDC2); and
superimposing the modulation signal onto the setpoint value for generating an adapted reference signal that is used for controlling switching of the semiconductor switches in order to balance DC link capacitor voltages (UDC1, UDC2) at the DC link capacitors (CDC1, CDC2).