US 12,231,032 B2
Pass gate driver
Bernhard Wolfgang Ruck, Freising (DE); Ruediger Kuhn, Freising (DE); and Oliver Nehrig, Freising (DE)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Dec. 21, 2023, as Appl. No. 18/391,809.
Application 18/391,809 is a continuation of application No. 17/560,756, filed on Dec. 23, 2021, granted, now 11,901,803.
Prior Publication US 2024/0128851 A1, Apr. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H02M 1/08 (2006.01); G05F 1/46 (2006.01); H02M 1/00 (2006.01)
CPC H02M 1/08 (2013.01) [G05F 1/46 (2013.01); H02M 1/0029 (2021.05)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first transistor having a control terminal coupled to a first node, a first current terminal coupled to a second node, and a second current terminal;
a second transistor having a control terminal, a first current terminal coupled to the second current terminal of the first transistor, and a second current terminal;
a third transistor having a control terminal, a first current terminal coupled to the second current terminal of the second transistor, and a second current terminal coupled to a third node;
a fourth transistor having a control terminal coupled to the first node, a first current terminal coupled to the second current terminal of the third transistor, and a second current terminal coupled to a fourth node;
a fifth transistor having a control terminal, a first current terminal coupled to the second current terminal of the first transistor, and a second current terminal;
a sixth transistor having a control terminal, a first current terminal coupled to the second current terminal of the fifth transistor, and a second current terminal coupled to the second current terminal of the second transistor;
a first circuit having a first terminal, a second terminal coupled to the second node, a third terminal, and a fourth terminal coupled to the fourth node; and
a second circuit having a first terminal coupled to the third terminal of the first circuit, and a second terminal coupled to the control terminal of the fifth transistor.