US 12,230,956 B2
Current limiting circuits
Haoran Li, Shenzhen (CN)
Assigned to TCL China Star Optoelectronics Technology Co., Ltd., Shenzhen (CN)
Appl. No. 17/605,024
Filed by TCL China Star Optoelectronics Technology Co., Ltd., Shenzhen (CN)
PCT Filed Jul. 27, 2021, PCT No. PCT/CN2021/108529
§ 371(c)(1), (2) Date Jan. 26, 2023,
PCT Pub. No. WO2023/000355, PCT Pub. Date Jan. 26, 2023.
Claims priority of application No. 202110816823.1 (CN), filed on Jul. 20, 2021.
Prior Publication US 2024/0022067 A1, Jan. 18, 2024
Int. Cl. H02H 9/02 (2006.01)
CPC H02H 9/02 (2013.01) 18 Claims
OG exemplary drawing
 
1. A current limiting circuit, comprising:
a first voltage terminal;
a second voltage terminal;
a first transistor, wherein an input terminal of the first transistor is electrically connected to the first voltage terminal, and an output terminal of the first transistor is electrically connected to the second voltage terminal; and
a current limiting module electrically connected to the input terminal of the first transistor and a control terminal of the first transistor,
wherein the current limiting module is configured to control voltage difference between the control terminal of the first transistor and the input terminal of the first transistor for controlling a state of the first transistor so that a current limiting value of the current limiting circuit is adjustable;
wherein the current limiting module comprises a second transistor, a first resistor, a third transistor, and a regulation unit,
wherein a first terminal of the second transistor is electrically connected to a first control terminal, a second terminal of the second transistor is electrically connected to the input terminal of the first transistor, and a third terminal of the second transistor is electrically connected to the control terminal of the first transistor,
wherein a first terminal of the first resistor is electrically connected to the input terminal of the first transistor, and a second terminal of the first resistor is electrically connected to the control terminal of the first transistor,
wherein a first terminal of the third transistor is electrically connected to a second control terminal, a second terminal of the third transistor is electrically connected to the control terminal of the first transistor, and a third terminal of the third transistor is connected to the regulation unit, and
wherein the regulation unit is configured to control the state of the first transistor.