US 12,230,721 B2
Gate-all-around integrated circuit structures having asymmetric source and drain contact structures
Biswajeet Guha, Hillsboro, OR (US); Mauro J. Kobrinsky, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Coporation, Santa Clara, CA (US)
Filed on Sep. 18, 2023, as Appl. No. 18/369,582.
Application 18/369,582 is a continuation of application No. 17/737,882, filed on May 5, 2022, granted, now 11,799,037.
Application 17/737,882 is a continuation of application No. 16/134,817, filed on Sep. 18, 2018, granted, now 11,367,796, issued on Jun. 21, 2022.
Prior Publication US 2024/0006541 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/786 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 21/823412 (2013.01); H01L 27/088 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/78651 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a vertical arrangement of nanowires above a fin;
a gate stack over and around the vertical arrangement of nanowires;
a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires, wherein the fin extends laterally beyond the first epitaxial source or drain structure;
a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires, wherein the fin does not extend laterally beyond the second epitaxial source or drain structure, wherein the first and second epitaxial source or drain structures are discrete first and second epitaxial source or drain structures;
a first conductive contact structure coupled to the first epitaxial source or drain structure; and
a second conductive contact structure coupled to the second epitaxial source or drain structure.