US 12,230,711 B2
Electronic device and method of manufacturing the same
Jinseong Heo, Seoul (KR); Sangwook Kim, Seongnam-si (KR); Yunseong Lee, Osan-si (KR); Sanghyun Jo, Seoul (KR); and Hyangsook Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 16, 2023, as Appl. No. 18/487,275.
Application 18/487,275 is a continuation of application No. 18/060,140, filed on Nov. 30, 2022, granted, now 11,824,118.
Application 18/060,140 is a continuation of application No. 17/001,979, filed on Aug. 25, 2020, granted, now 11,522,082, issued on Dec. 6, 2022.
Claims priority of application No. 10-2019-0114968 (KR), filed on Sep. 18, 2019.
Prior Publication US 2024/0038891 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/51 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/78391 (2014.09) [H01L 29/401 (2013.01); H01L 29/516 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a substrate;
a gate electrode on the substrate;
a ferroelectric crystallization layer between the gate electrode and the substrate, the ferroelectric crystallization layer being at least partially crystallized and including a dielectric material having ferroelectricity or anti-ferroelectricity;
a crystallization prevention layer between the ferroelectric crystallization layer and the substrate, the crystallization prevention layer including an amorphous dielectric material;
a high dielectric constant layer between the crystallization prevention layer and the substrate, the high dielectric constant layer including a different dielectric material than a material of the crystallization prevention layer; and
a high band gap layer between the high dielectric constant layer and the substrate, the high band gap layer including an amorphous dielectric material having a greater band gape than a material of the high dielectric constant layer.