US 12,230,706 B2
Transistor device having a cell field and method of fabricating a gate of the transistor device
Ingmar Neumann, Villach (AT); Michael Hutzler, Villach (AT); David Laforet, Villach (AT); Roland Moennich, Klagenfurt (AT); and Thomas Ralf Siemieniec, Villach (AT)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Jan. 30, 2023, as Appl. No. 18/102,831.
Application 18/102,831 is a continuation of application No. 17/163,744, filed on Feb. 1, 2021, granted, now 11,600,723.
Claims priority of application No. 20155979 (EP), filed on Feb. 6, 2020.
Prior Publication US 2023/0178647 A1, Jun. 8, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01)
CPC H01L 29/7813 (2013.01) [H01L 21/823462 (2013.01); H01L 29/0649 (2013.01); H01L 29/0696 (2013.01); H01L 29/401 (2013.01); H01L 29/404 (2013.01); H01L 29/407 (2013.01); H01L 29/42356 (2013.01); H01L 29/4236 (2013.01); H01L 29/42364 (2013.01); H01L 29/66666 (2013.01); H01L 29/66734 (2013.01); H01L 29/7811 (2013.01); H01L 29/7827 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A method of fabricating a gate of a transistor device that comprises a semiconductor substrate having a main surface, and a cell field comprising a plurality of transistor cells of a power transistor, the method comprising:
forming a gate trench in the main surface of the semiconductor substrate in the cell field;
forming a gate dielectric layer over the main surface of the semiconductor substrate and within the gate trench;
forming a metal gate electrode on the gate dielectric layer over the main surface of the semiconductor substrate and within the gate trench;
removing the metal gate electrode from the main surface of the semiconductor and partially over the gate trench such that a remainder of the metal gate electrode within the gate trench comprises an upper surface that is substantially coplanar with an upper surface of the gate dielectric layer formed over the main surface;
removing an upper portion of the remainder of the metal gate electrode from the gate trench such that an upper surface of the metal gate electrode is recessed within the gate trench;
forming an insulating layer on the recessed upper surface of the metal gate electrode and over the main surface of the semiconductor substrate; and
removing the insulating layer and the gate dielectric layer over the main surface and partially over the gate trench such that a remainder of the insulating layer forms an electrically insulating cap that comprises an upper surface that is substantially coplanar with the main surface of the semiconductor substrate,
before forming the gate dielectric layer, forming a dielectric layer at least on a bottom of the gate trench and over the main surface of the semiconductor substrate; and
when removing the insulating layer and the gate dielectric layer from the main surface, also removing the dielectric layer from the main surface.