| CPC H01L 29/7811 (2013.01) [H01L 21/02529 (2013.01); H01L 21/0465 (2013.01); H01L 21/0475 (2013.01); H01L 21/049 (2013.01); H01L 23/49 (2013.01); H01L 29/0623 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/402 (2013.01); H01L 29/66068 (2013.01); H01L 29/7813 (2013.01)] | 11 Claims |
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1. A semiconductor device having
an active region through which a main current flows,
a gate ring region surrounding a periphery of the active region,
a ring region surrounding a periphery of the gate ring region, and
a termination region surrounding a periphery of the ring region,
the semiconductor device comprising:
a semiconductor substrate of a first conductivity type, the semiconductor substrate having a front surface and a back surface opposite to each other;
a first semiconductor layer of the first conductivity type, provided at the front surface of the semiconductor substrate and having an impurity concentration lower than an impurity concentration of the semiconductor substrate, the first semiconductor layer having a first side and a second side opposite to each other, the second side facing the semiconductor substrate;
a second semiconductor layer of a second conductivity type, provided at a surface of the first semiconductor layer at the first side thereof, the second semiconductor layer having a first side and a second side opposite to each other, the second side of the second semiconductor layer facing the first semiconductor layer;
in the active region,
a plurality of first semiconductor regions of the first conductivity type, selectively provided in a surface layer of the second semiconductor layer at the first side thereof,
a gate insulating film having a first side and a second side opposite to each other, a surface thereof at the second side being in contact with the second semiconductor layer,
a plurality of first gate electrodes provided at a surface of the gate insulating film at the first side thereof,
an interlayer insulating film provided on the plurality of first gate electrodes,
a first first-electrode provided at a surface of the second semiconductor layer and surfaces of the plurality of first semiconductor regions, and
a first plating film selectively provided on the first first-electrode, and partially covering the first first-electrode in a depth direction of the semiconductor device;
in the gate ring region,
a first insulating film having a first side and a second side opposite to each other, a surface thereof at the second side being in contact with the second semiconductor layer, and
a second gate electrode provided at a surface of the first insulating film at the first side thereof, and
a gate wiring electrode provided on the second gate electrode;
in the ring region,
a second first-electrode provided at the surface of the second semiconductor layer and having an electric potential equal to that of the first first-electrode, the second first-electrode having a stacked structure that includes:
a NiSi layer provided on the surface of the second semiconductor layer,
a barrier metal provided on a surface of the NiSi layer, and
a film including Al provided on the barrier metal,
the barrier metal including a stack of four layers that respectively are, from the surface of the NiSi layer to the film including Al, a first TiN film, a first Ti film, a second TiN film, and a second Ti film, the second Ti film being in direct contact with the film including Al, and
a second plating film provided on the second first-electrode, and partially covering the second first-electrode in the depth direction of the semiconductor device; and
a second electrode provided at the back surface of the semiconductor substrate, wherein in a plan view of the semiconductor device,
the gate wiring electrode in the gate ring region forms a closed loop to fully surround the first first-electrode in the active region, and
the second first-electrode in the ring region forms another closed loop to fully surround the gate wiring electrode in the gate ring region;
the electric potential of the second first-electrode is fixed to that of the first first-electrode via the second semiconductor layer; and
the second plating film is spaced apart from the first plating film.
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