a semiconductor body comprising a barrier region of type III-V semiconductor material and a channel region of type III-V semiconductor material that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region near the heterojunction;

source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, each of the source and drain electrodes being in low-ohmic contact with the two-dimensional charge carrier gas channel;

a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas between the source and drain electrodes;

a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode;

a second dielectric region that covers the gate structure, wherein the second dielectric region has a different material composition as the first dielectric region;

a conductive field plate that is disposed over the semiconductor body in a region that is laterally between the between the gate structure and the drain electrode; and

a second conductive field plate that is disposed over the semiconductor body in a region that is laterally between the between the gate structure and the drain electrode,

wherein the second conductive field plate is disposed on a third dielectric region that is formed on the field plate,

wherein the first dielectric region comprises aluminum and oxide,

wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.