US 12,230,698 B2
Thyristor, triac and transient-voltage-suppression diode manufacturing
Patrick Hauttecoeur, Saint Cyr sur Loire (FR); and Vincent Caro, Chambray les Tours (FR)
Assigned to STMicroelectronics (Tours) SAS, Tours (FR)
Filed by STMicroelectronics (Tours) SAS, Tours (FR)
Filed on Feb. 15, 2023, as Appl. No. 18/110,095.
Application 18/110,095 is a division of application No. 17/188,826, filed on Mar. 1, 2021, granted, now 11,610,988.
Claims priority of application No. 2002211 (FR), filed on Mar. 5, 2020.
Prior Publication US 2023/0197835 A1, Jun. 22, 2023
Int. Cl. H01L 29/747 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/747 (2013.01) [H01L 29/0661 (2013.01); H01L 29/66386 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A method of manufacturing a device, comprising:
forming a step at a periphery of a semiconductor substrate;
forming a first layer on top of and in contact with a first surface of the semiconductor substrate, the first layer extending at least on and in contact with walls and bottoms of said step;
wherein the first layer is made of polysilicon doped with oxygen; and
forming a second layer extending on and in contact with an upper surface of the first layer and extending on and in contact with an edge of the first layer to form, between the step and a central portion of the device, a boss;
wherein the second layer is made of glass;
wherein the forming of the second layer comprises:
forming a first glass sub-layer on and in contact with the first layer;
first wet etching of the first layer and the first glass sub-layer along a pattern of a first mask formed by photolithography;
forming a second glass sub-layer on and in contact with the first glass sub-layer so that the second glass sub-layer covers the first glass sub-layer and edges of the first layer and the first glass sub-layer, to form the boss at an inner periphery of the step; and
second wet etching of the second sub-layer along a pattern of a second mask formed by photolithography.