| CPC H01L 29/7397 (2013.01) [H01L 29/1608 (2013.01); H01L 29/4236 (2013.01); H01L 29/66325 (2013.01)] | 26 Claims | 

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               1. A semiconductor device, comprising 
            an N+ type substrate; 
                an N− type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate; 
                a P type region disposed in the N− type layer and disposed on a side surface of the trench; 
                a gate electrode disposed in the trench; and 
                a source electrode and a drain electrode insulated from the gate electrode, 
                wherein the N− type layer includes a P type shield region covering a bottom surface and an edge of the trench, 
                wherein the N− type layer includes an N type current diffusion region disposed on a side surface of the trench, 
                wherein the trench includes 
              a first trench region disposed in the P type region and having a first width, and 
                  a second trench region disposed in the N− type layer and having a second width, wherein the first width of the first trench region is wider than the second width of the second trench region. 
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