US 12,230,696 B2
Semiconductor device and method for fabricating the same
Shunpei Yamazaki, Tokyo (JP); Hideomi Suzawa, Kanagawa (JP); Shinya Sasagawa, Kanagawa (JP); Motomu Kurata, Kanagawa (JP); and Masashi Tsubuku, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Mar. 15, 2024, as Appl. No. 18/606,052.
Application 16/194,444 is a division of application No. 15/461,575, filed on Mar. 17, 2017, granted, now 10,134,879, issued on Nov. 20, 2018.
Application 15/461,575 is a division of application No. 14/021,618, filed on Sep. 9, 2013, granted, now 9,601,632, issued on Mar. 21, 2017.
Application 18/606,052 is a continuation of application No. 17/902,224, filed on Sep. 2, 2022, granted, now 11,935,944.
Application 17/902,224 is a continuation of application No. 17/167,332, filed on Feb. 4, 2021, granted, now 11,437,500, issued on Sep. 6, 2022.
Application 17/167,332 is a continuation of application No. 16/671,612, filed on Nov. 1, 2019, granted, now 10,923,580, issued on Feb. 16, 2021.
Application 16/671,612 is a continuation of application No. 16/194,444, filed on Nov. 19, 2018, granted, now 10,468,506, issued on Nov. 5, 2019.
Claims priority of application No. 2012-203385 (JP), filed on Sep. 14, 2012.
Prior Publication US 2024/0274696 A1, Aug. 15, 2024
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 27/146 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66969 (2013.01) [H01L 21/02565 (2013.01); H01L 27/1225 (2013.01); H01L 27/127 (2013.01); H01L 27/14616 (2013.01); H01L 27/14689 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of circuits:
the plurality of circuits each comprising:
a first transistor comprising a channel formation region comprising an oxide semiconductor;
a second transistor comprising a channel formation region comprising silicon; and
a capacitor,
wherein a source or a drain of the first transistor is electrically connected to a gate of the second transistor, and
wherein the gate of the second transistor is electrically connected to the capacitor,
a first conductive layer;
an oxide semiconductor layer comprising a region over the first conductive layer;
a first insulating layer comprising a region over the oxide semiconductor layer;
a second conductive layer comprising a region over the first insulating layer; and
a second insulating layer comprising a region over the second conductive layer,
wherein the first conductive layer comprises a region functioning as one of a source electrode and a drain electrode of the first transistor,
wherein the oxide semiconductor layer comprises a region configured to function as the channel formation region of the first transistor,
wherein the first insulating layer comprises a region configured to function as a gate insulating layer of the first transistor,
wherein the second conductive layer comprises a region configured to function as a gate electrode of the first transistor,
wherein the oxide semiconductor layer is in contact with part of a top surface and a side surface of the first conductive layer,
wherein in a cross-sectional view of the first transistor along a channel length direction, the first insulating layer comprises an extended region extending beyond an end portion of the second conductive layer,
wherein the second insulating layer is an oxide insulating layer,
wherein the second insulating layer comprises a region in contact with the top surface of the extended region of the first insulating layer, a region in contact with a side surface of the first insulating layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with the top surface of the first conductive layer, and
wherein a width of the first conductive layer in a channel width direction of the first transistor is larger than a channel width of the first transistor in the channel formation region.
 
2. A semiconductor device comprising:
a plurality of circuits:
the plurality of circuits each comprising:
a first transistor comprising a channel formation region comprising an oxide semiconductor;
a second transistor comprising a channel formation region comprising silicon; and
a capacitor,
wherein a source or a drain of the first transistor is electrically connected to a gate of the second transistor, and
wherein the gate of the second transistor is electrically connected to the capacitor,
a first conductive layer;
an oxide semiconductor layer comprising a region over the first conductive layer;
a first insulating layer comprising a region over the oxide semiconductor layer;
a second conductive layer comprising a region over the first insulating layer; and
a second insulating layer comprising a region over the second conductive layer,
wherein the first conductive layer comprises a region functioning as one of a source electrode and a drain electrode of the first transistor,
wherein the oxide semiconductor layer comprises a region configured to function as the channel formation region of the first transistor,
wherein the first insulating layer comprises a region configured to function as a gate insulating layer of the first transistor,
wherein the second conductive layer comprises a region configured to function as a gate electrode of the first transistor,
wherein the oxide semiconductor layer is in contact with part of a top surface and a side surface of the first conductive layer,
wherein in a cross-sectional view of the first transistor along a channel length direction, the first insulating layer comprises an extended region extending beyond an end portion of the second conductive layer,
wherein the second insulating layer is an oxide insulating layer,
wherein the second insulating layer comprises a region in contact with the top surface of the extended region of the first insulating layer, a region in contact with a side surface of the first insulating layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with the top surface of the first conductive layer,
wherein a width of the first conductive layer in a channel width direction of the first transistor is larger than a channel width of the first transistor in the channel formation region,
wherein the oxide semiconductor layer comprises a first layer and a second layer over the first layer,
wherein the first layer and the second layer each comprises indium, gallium, and zinc, and
wherein an atomic ratio of indium, gallium and zinc in the first layer is different from that of the second layer.