US 12,230,695 B2
Display substrate and manufacturing method thereof, display device
Meng Zhao, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Jun. 21, 2023, as Appl. No. 18/338,421.
Application 18/338,421 is a continuation of application No. 17/355,380, filed on Jun. 23, 2021, granted, now 11,728,416.
Claims priority of application No. 202011329036.6 (CN), filed on Nov. 24, 2020.
Prior Publication US 2023/0335624 A1, Oct. 19, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66969 (2013.01) [H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 27/127 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A display substrate, comprising a base substrate and a first thin film transistor on the substrate; wherein
the first thin film transistor comprises a first gate on the base substrate, and a first gate insulating layer on a side of the first gate distal to the base substrate;
an active layer of the first thin film transistor is on a side of the first gate insulating layer distal to the base substrate; a second gate insulating layer is on a side of the active layer of the first thin film transistor distal to the base substrate;
a second gate of the first thin film transistor is on a side of the second gate insulating layer distal to the base substrate, and an orthographic projection of the second gate of the first thin film transistor on the base substrate is in an orthographic projection of the active layer of the first thin film transistor on the base substrate; a first interlayer insulating layer is on a side of the second gate of the first thin film transistor distal to the base substrate;
a source, a drain of the first thin film transistor and a gate line are on a side of the first interlayer insulating layer distal to the base substrate, and the source and the drain of the first thin film transistor are respectively connected to the active layer of the first thin film transistor through a source contact via and a drain contact via penetrating through the first interlayer insulating layer; the gate line is electrically connected to the second gate of the first thin film transistor through a first connection via penetrating through the first interlayer insulating layer; and
the gate line is electrically connected to the first gate of the first thin film transistor to receive a gate signal through a second connection via penetrating through the first interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.