US 12,230,694 B2
Method for making nanostructure transistors with source/drain trench contact liners
Donghun Kang, San Jose, CA (US)
Assigned to ATOMERA INCORPORATED, Los Gatos, CA (US)
Filed by Atomera Incorporated, Los Gatos, CA (US)
Filed on Mar. 22, 2024, as Appl. No. 18/613,557.
Claims priority of provisional application 63/507,578, filed on Jun. 12, 2023.
Claims priority of provisional application 63/492,038, filed on Mar. 24, 2023.
Prior Publication US 2024/0322015 A1, Sep. 26, 2024
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/15 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66742 (2013.01) [H01L 29/0603 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/15 (2013.01); H01L 29/158 (2013.01); H01L 29/16 (2013.01); H01L 29/161 (2013.01); H01L 29/41733 (2013.01); H01L 29/41741 (2013.01); H01L 29/41766 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H01L 29/151 (2013.01); H01L 29/42392 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for making a semiconductor device comprising:
forming a plurality of spaced apart gate stacks on a substrate with adjacent gate stacks defining a respective trench therebetween, each gate stack comprising alternating layers of first and second semiconductor materials, the layers of the second semiconductor material defining nanostructures;
forming respective source/drain regions within the trenches;
forming respective insulating regions adjacent lateral ends of the layers of the first semiconductor material;
forming respective conductive contact liners in the trenches; and
forming a respective metal plug in each trench adjacent the conductive contact liner.