US 12,230,692 B2
Self-aligned inner spacer on gate-all-around structure and methods of forming the same
Tsungyu Hung, Hsinchu (TW); Pang-Yen Tsai, Hsin-Chu Hsian (TW); and Pei-Wei Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,597.
Application 17/182,651 is a division of application No. 16/439,909, filed on Jun. 13, 2019, granted, now 10,930,755, issued on Feb. 23, 2021.
Application 18/359,597 is a continuation of application No. 17/182,651, filed on Feb. 23, 2021, granted, now 11,749,742.
Claims priority of provisional application 62/771,334, filed on Nov. 26, 2018.
Prior Publication US 2023/0387253 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/66553 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02247 (2013.01); H01L 21/02252 (2013.01); H01L 21/02255 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/66545 (2013.01); H01L 29/6681 (2013.01); H01L 29/7853 (2013.01); H01L 21/30604 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
16. A device comprising:
a first semiconductor layer disposed on a substrate;
a second semiconductor layer disposed over the first semiconductor layer such that the second semiconductor layer is spaced apart from the first semiconductor layer;
an inner spacer extending from the first semiconductor layer to the second semiconductor layer, the inner spacer formed of remnants of at least one of the first and second semiconductor layers;
a source/drain feature interfacing with at least a portion of the inner spacer; and
a gate structure disposed on and wrapping around the first and second semiconductor layers, the gate structure including a gate dielectric layer having a first portion wrapping around the first and second semiconductor layers and a second portion disposed directly on a top surface of the inner spacer, the top surface of the inner spacer facing way from the substrate.