US 12,230,691 B2
Three dimensional device formation using early removal of sacrificial heterostructure layer
Yan Zhang, Westford, MA (US); Johannes M. van Meer, Middleton, MA (US); Sankuei Lin, Los Gatos, CA (US); Baonian Guo, Andover, MA (US); and Naushad K. Variam, Marblehead, MA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on May 13, 2022, as Appl. No. 17/744,238.
Prior Publication US 2023/0369453 A1, Nov. 16, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66545 (2013.01) [H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66553 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
11. A method for forming a nanosheet device, comprising:
forming a heterostructure device stack on a semiconductor fin, the heterostructure device stack comprising a set of silicon layers arranged in a vertical stack and in alternating fashion with a set of SiGe layers;
patterning the heterostructure device stack to define a dummy gate region, disposed over the semiconductor fin;
selectively removing the set of SiGe layers of the heterostructure device stack within the dummy gate region; and
after the selectively removing, forming a source/drain structure adjacent to the dummy gate region.