US 12,230,690 B2
Method of forming a high electron mobility transistor
Chun-Wei Hsu, Taichung (TW); Jiun-Lei Jerry Yu, Hsinchu County (TW); Fu-Wei Yao, Hsinchu (TW); Chen-Ju Yu, Yilan County (TW); Fu-Chih Yang, Kaohsiung County (TW); and Chun Lin Tsai, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 27, 2023, as Appl. No. 18/360,694.
Application 15/192,889 is a division of application No. 13/338,962, filed on Dec. 28, 2011, granted, now 9,379,191, issued on Jun. 28, 2016.
Application 18/360,694 is a continuation of application No. 17/303,331, filed on May 26, 2021, granted, now 11,804,538.
Application 17/303,331 is a continuation of application No. 16/947,616, filed on Aug. 10, 2020, granted, now 11,404,557, issued on Aug. 2, 2022.
Application 16/947,616 is a continuation of application No. 16/101,065, filed on Aug. 10, 2018, granted, now 10,741,665, issued on Aug. 11, 2020.
Application 16/101,065 is a continuation of application No. 15/645,463, filed on Jul. 10, 2017, granted, now 10,050,117, issued on Aug. 14, 2018.
Application 15/645,463 is a continuation of application No. 15/192,889, filed on Jun. 24, 2016, granted, now 9,704,968, issued on Jul. 11, 2017.
Prior Publication US 2023/0369449 A1, Nov. 16, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/267 (2006.01); H01L 29/417 (2006.01); H01L 29/43 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/66462 (2013.01) [H01L 21/02271 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01); H01L 29/267 (2013.01); H01L 29/41766 (2013.01); H01L 29/432 (2013.01); H01L 29/7786 (2013.01); H01L 2924/0002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor transistor device, the device comprising:
a first III-V compound layer;
a second III-V compound layer disposed over the first III-V compound layer and different from the first III-V compound layer in composition;
a dielectric layer over the second III-V compound layer;
a source feature disposed over the second III-V compound layer and the dielectric layer, wherein an upper surface of the source feature extends a first width and a lower surface extends a second width, wherein the source feature extends into a first opening in the dielectric layer; and
a gate electrode extending into a second opening in the dielectric layer.