| CPC H01L 29/66462 (2013.01) [H01L 21/02381 (2013.01); H01L 21/0254 (2013.01); H01L 21/7806 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/41758 (2013.01); H01L 29/7786 (2013.01)] | 10 Claims |

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1. A method for fabricating a semiconductor wafer, the method comprising:
epitaxially growing a III-V semiconductor on a first surface of a foreign wafer having a thickness tw, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, the foreign wafer having a second surface opposing the first surface;
removing portions of the III-V semiconductor to produce a plurality of mesas comprising the III-V semiconductor arranged on the first surface of the foreign wafer;
applying an insulation layer to regions of the foreign wafer arranged between the mesas; and
progressively removing portions of the second surface of the foreign wafer, exposing the insulation layer in regions adjacent the mesas and producing a worked second surface,
wherein the applying an insulation layer comprises:
depositing the insulation layer onto the mesa and regions between the mesas such that the insulation layer has a thickness that is at least as great as a height of the mesas and the mesas are covered with the insulation layer; and
planarising the insulation layer and forming a planarised surface comprising an upper surface of the mesa and an upper surface of the insulation layer.
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