US 12,230,681 B2
Semiconductor memory devices with different doping types
Meng-Sheng Chang, Chubei (TW); Chia-En Huang, Xinfeng Township (TW); Chun Chung Su, New Taipei (TW); and Wen-Hsing Hsieh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 22, 2023, as Appl. No. 18/518,142.
Application 18/518,142 is a continuation of application No. 17/477,196, filed on Sep. 16, 2021, granted, now 11,856,761.
Claims priority of provisional application 63/185,526, filed on May 7, 2021.
Prior Publication US 2024/0090210 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/41 (2006.01); G11C 11/402 (2006.01); G11C 17/12 (2006.01); G11C 17/16 (2006.01); H01L 23/00 (2006.01); H10B 20/00 (2023.01); H10B 20/25 (2023.01)
CPC H01L 29/413 (2013.01) [G11C 17/12 (2013.01); G11C 17/123 (2013.01); G11C 17/16 (2013.01); G11C 17/165 (2013.01); H10B 20/25 (2023.02); H10B 20/30 (2023.02); H10B 20/367 (2023.02); H10B 20/60 (2023.02); G11C 11/4023 (2013.01); H01L 23/573 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor including a first gate structure wrapping around a first conduction channel, the first conduction channel disposed between a first drain/source structure and a second drain/source structure; and
a second transistor including a second gate structure wrapping around a second conduction channel, the second conduction channel disposed between the second drain/source structure and a third drain/source structure, wherein:
the first drain/source structure and the second drain/source structure have opposite doping types, and
the first drain/source structure and the third drain/source structure have the same doping type.